Typically, a semiconductor wafer is patterned and processed to create a plurality of integrated circuits. The individual dies are separated from one another by scribe lines that encompass each die and are formed during the patterning process. At the end of the wafer-level processing, each die includes a complete set of circuitry, and typically includes a set of test pads and/or bond pads that a bed-of-nails semiconductor test set-up can use to electrically communicate with the circuitry of each die. In this way, it is possible to perform wafer-level electrical test of the circuitry to eliminate from further processing at least some of the die failures before packaging the individual dies.
The conventional wafer is then shipped, to a “back end” manufacturing facility, whereupon the wafer is sawed or cut along the scribe lines to produce singulated dies. The singulated dies, or “chips,” are then mounted in lead frames and connected to the leads of the lead frame by bond wires. Finally, the assemblies are encapsulated in packages, typically within plastic or ceramic chip packages to form a packaged semiconductor.
In conventional semiconductor processing, a fully processed semiconductor wafer is coated with a protective layer of oxide prior to the wafer being sawed into individual dies. Thus, each individual die is protected from damage that may otherwise be caused by the debris particles generated during the sawing. The scribe lines also serve to seal each integrated circuit from the next so that there is no ion contamination of each circuit form the wafer saw break. The scribe lines are also used to provide alignment of reticles used during the repeated integrated circuit patterning process.
Electromechanical devices, including MEMS devices and in specific embodiments, optical devices such as Digital Micromirror Devices (“DMDs”), however, generally are not protected with an oxide layer at the wafer level, and in such instances will not be similarly protected from sawing debris and other contamination. The individual mirrors of the DMD mirror array are susceptible to damage from debris, including particles generated during the wafer saw-and-break or full-saw process. Because the DMD is a micromechanical device with movable pixel mirrors, the DMDs fabricated upon a wafer may not be conveniently covered with a protective oxide coating prior to a saw process as is conventional for to other semiconductor processing techniques. Moreover, due to the conductive address electrodes which are positioned below the conductive mirrors, a conductive particle entrapped between the mirror and address electrode could short the micromirror to the address electrode.
Certain techniques for minimizing particulate damage to DMD mirrors or other MEMS structures were disclosed in commonly assigned U.S. Pat. No. 5,435,876 entitled Grid Array Masking Tape Process. Technique disclosed therein included using a grid array masking tape over the active surface of the processed wafer. The tape would adhere to the wafer along a grid extending between the formed integrated circuits to prevent debris from damaging the active surface of the devices during the sawing process. The tape was removed after the saw process and then a photoresist, which had also remained under the mirror layer during the sawing was removed by a plasma etch.
Another prior-art method of dealing with contamination issues includes the application of temporary resist layers over the MEMS-type structures or DMD micromirrors to protect them from damage from debris or other environmental factors. Examples of this approach are described in commonly assigned U.S. Pat. Nos. 5,083,857 and 6,063,696. Another method is to cover all the dies on a wafer with a lid wafer or with another cover. Examples of this approach are described in U.S. Pat. Nos. 5,798,557 and 5,915,168.